Function comb_mod
pub extern fn comb_mod<T>(x: T, y: T) -> TExpand
Evaluates to x % y in Verilog.
In general, this is going to be slow and large, so it should be avoided if you don’t know what
you’re doing. For modulo operations by a constant power of two, use % instead.
Examples
assert (6u8 `comb_mod` 3) == 0;
assert (7u8 `comb_mod` 3) == 1;Requires T to be Number. This requirement is enforced by the compiler but not part of the type
signature for now